This core implements an area-efficient Viterbi decoder using a Trace-back method for survivor memory. In order to achieve an area reduction each ACSU is used as two nodes of the trellis. Therefore, two clock cycles are needed to process one input symbol. Its more important features and implementation example results are shown below.
Viterbi Decoder core features:
- Configurable constraint length: 7, 8 or 9
- Configurable rate: 1/2 or 1/3
- Configurable soft input data width from 2 to 12
- Configurable data-path width from 4 to 16
- Configurable trace-back length from 20 to 256
- Configurable generator polynomials
- Branch-Metrics can be normalized
Implementation example
The Viterbi Decoder core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:
- Contraint length (K)= 7 and 9
- Rate= 1/12
- 4-bit width soft input data
- 8-bit width data-path
- Trace-back length= 60
- Generator Polynomials= (1111001,1011011) for K=7 and (111101011,101110001) for K=9
The following table shows the implementation results for the Virtex-6 device:
|
K=7
|
K=9
|
|
|---|---|---|
|
Number of slices
|
738
|
2,204
|
|
Number of RAMB36E1
|
1
|
4
|
|
Max. Clock Frequency
|
279.1 MHz
|
251.3 MHz
|
|
Throughput
|
139.5 Mbps
|
125.6 Mbps
|
The following table shows the implementation results for the Stratix-IV device:
|
K=7
|
K=9
|
|
|---|---|---|
|
Total LABs
|
155
|
603
|
|
M9K blocks
|
2
|
8
|
|
Max. Clock Frequency
|
290.7 MHz
|
238.6 MHz
|
|
Throughput
|
145.3 Mbps
|
119.3 Mbps
|