The main research line is the development of algorithms and architectures for implementing digital signal processing and communication systems on FPGA.
- Algorithms and architectures for advanced Forward Error Correction (FEC)
- OFDM-based Optical CommunicationS Systems
- Algorithms and architectures for FPGA-based software radios
- FPGA-based DSP for ultrasound waves
- High performance arithmetic and DSP operators for FPGA
The objective of this research is the development of algorithms and architectures for hardware implementation of FEC blocks that will be required in future communications systems.
We have focused in:
- Binary Low-Density Parity-Check codes decoders
- Non-binary Low-Density Parity-Check codes decoders
- Soft decoding of Reed-Solomon codes.
We want to improve the operation of the LDPC decoders for high SNRs where the error-floor can appears. We have developed an FPGA-based hardware LDPC emulator to accelerate simulations for very low bit rates.
The use of the OFDM modulation in optical communication has attracted a high interest in recent years thanks to the possibility of simple equalization with moderate implementation complexity using digital signal processing techniques. The objectives of this research line are:
- Development of algorithms for direct detection optical OFDM
- Analysis and evaluation of nonlinear optical effects in optical OFDM
- Implementation of a real-time demonstrator using high speed data converters (Gsps)
Algorithms and architectures for FPGA-based software radios Algorithms and architectures to implement digital communication systems in FPGA devices:
- Re-sampling for transmission
- Digital up & down conversion
- Synchronization for QAM systems
- Synchronization for OFDM systems
- Digitally implemented analog modulations
Three FPGA-based demonstrators have been developed:
Ultrasounds are used in non-destructive measurements in nuclear and aeronautic sectors. This line is focused in the design of digital signal processing algorithms for ultrasound waves and their hardware architectures for FPGA devices:
- FIR and IIR Filters
- Multirate filters
- Pipeline-interleaved filters
- Envelope detectors
- Logarithmic converters
- Interpolators for Giga-sample operation
- Beanforming for array sensors
This R&D line is developed for the company TECNATOM under the contract “Desarrolllos de tecnologías electrónicas”.
Design of arithmetic operators and digital signal processing kernels optimized for their implementation in Altera and Xilinx FPGA devices.