Time Recovery Loop (IP core)

This core implements a time recovery loop for QAM demodulation based on a Lagrange coefficients fractional interpolator and Gardner timing error detector. Its more important features and implementation example results are shown below.

Time Recovery Loop core features:

  • Valid for QAM modulations
  • Valid for any input sample rate between 2 and 4
  • Internal PI loop control

Implementation example

The Time Recovery Loop core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4).

The following table shows the implementation results for the Virtex-6 device:

Results
Number of slices
248
Number of DSP48E1s
14
Max. Clock Frequency
212.1 MHz

The following table shows the implementation results for the Stratix-IV device:

Results
Total LABs
99
DSP block 18-bit elements
24
Max. Clock Frequency
255.1 MHz