This core implements a serial Reed-Solomon decoder for 8-bit wide symbols. It can correct both errors and erasures. Its more important features and implementation example results are shown below.
Reed-Solomon Decoder core features:
- Configurable Primitive Polynomial
- Variable number of parity symbols (t) from 4 to 10
- Variable Generator Polynomial power value
- Valid for shortened length codes, from 54 to full length (255)
- Maximum number of errors/2 + erasures ≤ t
Implementation example
The Reed-Solomon Decoder core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:
- Primitive polynomial = 285 and 391
The following table shows the implementation results for the Virtex-6 device:
|
Pol=285
|
Pol=391
|
|
|---|---|---|
|
Number of slices
|
339
|
336
|
|
Number of RAMB18E1
|
2
|
2
|
|
Max. Clock Frequency
|
228.8 MHz
|
229.7 MHz
|
|
Throughput
|
91.5 Mbps
|
91.8 Mbps
|
The following table shows the implementation results for the Stratix-IV device:
|
Pol=285
|
Pol=391
|
|
|---|---|---|
|
Total LABs
|
98
|
104
|
|
M9K blocks
|
1
|
1
|
|
Max. Clock Frequency
|
201.9 MHz
|
205.5 MHz
|
|
Throughput
|
80.7 Mbps
|
82.2 Mbps
|