This core implements a phase recovery loop for QPSK demodulation based on a Costas loop phase detector. Its more important features and implementation example results are shown below.
Phase Recovery Loop core features:
- Valid for QPSK modulations
- Internal PI loop control
Implementation example
The Phase Recovery Loop core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4).
The following table shows the implementation results for the Virtex-6 device:
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Results
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|---|---|
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Number of slices
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164
|
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Number of RAMB36E1
|
1
|
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Number of DSP48E1s
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12
|
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Max. Clock Frequency
|
195.3 MHz
|
The following table shows the implementation results for the Stratix-IV device:
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Results
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|---|---|
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Total LABs
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82
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DSP block 18-bit elements
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23
|
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Max. Clock Frequency
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248.5 MHz
|