This core implements a compensated linear to logarithm converter. The core is implemented with the log(1+x) ≈ x approximation and a correction factor. Its more important features and implementation example results are shown below.
Linear-Logarithm Converter core features:
- Configurable input data width: 16-bit or 20-bit
- Fully pipelined: 7 clock cycles latency
Implementation example
The Linear-Logarithm Converter core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:
- Input data width = 16-bit and 20-bit
The following table shows the implementation results for the Virtex-6 device:
|
16-bit
|
20-bit
|
|
|---|---|---|
|
Number of slices
|
166
|
177
|
|
Number of DSP48E1s
|
2
|
5
|
|
Max. Clock Frequency
|
201.1 MHz
|
196.0 MHz
|
The following table shows the implementation results for the Stratix-IV device:
|
16-bit
|
20-bit
|
|
|---|---|---|
|
Total LABs
|
29
|
34
|
|
DSP blocks 18-bit
|
4
|
7
|
|
Max. Clock Frequency
|
258.3 MHz
|
201.6 MHz
|