This core implements an LDPC decoder based on the Memory-Based Partially-Parallel architecture for unitary weight sub-matrix structured LDPC codes. The core implements the normalized Min-Sum algorithm that performs nearly the performance of the floating point Belief-Propagation algorithm. Its more important features and implementation example results are shown below.
LDPC Decoder core features:
- Configurable LDPC code (unitary weight sub-matrix structured code)
- Configurable input data width from 2 to 12
- Configurable internal data width from 2 to 12
- Variable number of iterations (externally controlled using iteration counter output signal)
- Early termination signal (Parity Check)
- LLR or Received symbols input
- Allows regular and irregular LDPC codes
Implementation example
The LDPC Decoder core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:
- LDPC Code from the 802.3an Standard – Regular (2048,1723)
- 6-bit width LLR input
- 6-bit width internal data
- Max. Number of iterations = 30
The following table shows the implementation results for the Virtex-6 device:
Results
|
|
---|---|
Number of slices
|
6,499
|
Number of RAMB18E1
|
1
|
Max. Clock Frequency
|
357.6 MHz
|
Throughput (@30 iterations)
|
169.5 Mbps
|
Throughput (@16 iterations)
|
317.8 Mbps
|
The following table shows the implementation results for the Stratix-IV device:
Results
|
|
---|---|
Total LABs
|
2,027
|
M9K blocks
|
367
|
Max. Clock Frequency
|
278.4 MHz
|
Throughput (@30 iterations)
|
131.9 Mbps
|
Throughput (@16 iterations)
|
247.4 Mbps
|