The CORDIC core implements a COordinate Rotation DIgital Computer (CORDIC) operator. It has various implementation types: rotation mode/circular coordinate, vectoring mode/circular coordinate, rotation mode/linear coordinate, vectoring mode/linear coordinate, dual-mode/circular coordinate, dual-mode/linear coordinate and dual-mode/dual coordinate. Each implementation type can be fully pipelined or unregistered. Its main paramameters and an example to show the performance are below.
CORDIC core features:
- Rotation mode (RM), Vectoring mode (VM) or both (RVM)
- Linear coordinate(LC), Circular coordinate (CC) or both (LCC)
- Combinatorial or Fully Pipelined behavior
- Vectors (X,Y) data-path word-length
- Angle (Z) data-path word-length
- Scaled or non scaled output
Implementation example
The different implementation types for the CORDIC core were implemented in a Virtex-4 device (speed grade -12) using the following features:
- X,Y and Z data-path word-length of 16 bits
- 16 iterations
The following table shows the area and maximum throughput achieved by the core implementations.
Architecture
|
Area [slices]
|
Throughput [MHz]
|
---|---|---|
rotation mode/circular coordinate
|
461
|
327
|
vectoring mode/circular coordinate
|
461
|
328
|
rotation mode/linear coordinate
|
417
|
329
|
vectoring mode/linear coordinate
|
417
|
329
|
dual-mode/circular coordinate
|
510
|
323
|
dual-mode/linear coordinate
|
464
|
323
|
dual-mode/dual coordinate
|
551
|
332
|
Results for the dual-mode/dual coordinate implemented using RPM, RTL and Behavioral methods in Xilinx Virtex4 and Altera Stratix II devices are shown next.
Device
|
RPM
|
RTL
|
Behavioral
|
---|---|---|---|
Xilinx Virtex4 -12
pipelined |
551 slices/322 MHz
|
576 slices/262 MHz
|
770 slices/197 MHz
|
Altera Stratix II -3
pipelined |
N/A
|
1036 ALUTs/322 MHz
|
1227 ALUTs/205 MHz
|
Xilinx Virtex4 -12
combinatorial |
493 slices/22 MHz
|
555 slices/21 MHz
|
741 slices/17 MHz
|
Altera Stratix II -3
combinatorial |
N/A
|
945 ALUTs/21 MHz
|
1090 ALUTs/18 MHz
|
The next figure shows the layout for a fully pipelined CORDIC implementation using RPM in a Virtex-4 device.