CMA Equalizer (IP core)

This core implements a configurable tap fractionally-spaced blind adaptive equalizer based on the constant modulus algorithm (CMA) for quadrature amplitude modulation (QAM) signals. Its more important features and implementation example results are shown below.

CMA Equalizer core features:

  • Configurable number of taps from 4 to 32
  • Programable initial conditions
  • Valid for BPSK, QPSK and 16-QAM modulations
  • Variable number of samples per symbol

Implementation example

The CMA Equalizer core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:

  • Number of taps = 16, 24 and 32
  • Modulation = QPSK
  • 17 bits input and output data
  • 1 and 2 samples per symbol

The following table shows the implementation results for the Virtex-6 device:

16-taps
24-taps
32-taps
Number of slices
1,429
1,930
2,765
Number of DSP48E1s
54
78
102
Max. Clock Frequency
72.2 MHz
72.0 MHz
69.4 MHz
Throughput @1sps
14.4 Msps
14.4 Msps
13.8 Msps
Throughput @2sps
7.2 Msps
7.2 Msps
6.9 Msps

The following table shows the implementation results for the Stratix-IV device:

16-taps
24-taps
32-taps
Total LABs
441
656
896
DSP block 18-bit elements
108
156
204
Max. Clock Frequency
87.9 MHz
79.4 MHz
78.6 MHz
Throughput @1sps
17.5 Msps
15.8 Msps
15.7 Msps
Throughput @2sps
8.7 Msps
7.9 Msps
7.8 Msps