This core implements an logarithm-based Digital Automatic Gain Control with PI control. Its more important features and implementation example results are shown below.
Digital AGC core features:
- Variable power estimator decimation factor
- Variable power estimator average factor
- Variable threshold
- Open and close loop operation modes
- Kp and Ki variable values for close loop mode
- Variable Gain for open loop mode
Implementation example
The Digital AGC core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:
- 32-bit width input data
- 16-bit width output data
The following table shows the implementation results for the Virtex-6 device:
Results
|
|
---|---|
Number of slices
|
234
|
Number of RAMB18E1
|
4
|
Number of DSP48E1s
|
6
|
Max. Clock Frequency
|
228.8 MHz
|
The following table shows the implementation results for the Stratix-IV device:
Results
|
|
---|---|
Total LABs
|
110
|
DSP blocks 18-bit
|
12
|
Max. Clock Frequency
|
206.4 MHz
|