Conference papers

  • R. Llorente, M. Morant, J. S. Bruno and V. Almenar ,”Software-defined beamforming enabled by spatial division multiplexing in the multicore fiber optical fronthaul”, : invited paper in SPIE OPTO Photonics West 2020, 2020
  • Vallejo-Castro, Luis; Ortega Tamarit, Beatriz; Zvanovec, Stanislav; Bohata, Jan; Almenar Terre, Vicenç (2019). «Experimental photonic 40-90 GHz millimetre-wave signal generation and 32-QAM signal transmission over hybrid fiber/FSO 5G networks». 21th International Conference on Transparent Optical Networks (ICTON 2019). (1 – 4). Angers, France: IEEE
  • M. Morant; J. S. Bruno; V. Almenar; R. Llorente , “Performance evaluation of OFDM and SC-QAM backhaul provision on FTTH optical access networks including multi-core fiber riser”, SPIE Photonics West 2019 – Broadband Access Communication Technologies XIII, 2019
  • G. Perrone, J. Valls, V. Torres, F. García-Herrero, “High-throughput onechannel RS(255,239) Decoder,” 16th 21st Euromicro Conference on Digital System Design, pp. 110-114, Prague, Czech Republic, Aug. 2018
  • V. Torres, J. Valls, M.J. Canet, F. García-Herrero, “Soft-decision LCC Decoder Architecture with _=4 for RS(255,239),” 16th IEEE International NEWCAS Conference, pp. 305-308, Montreal, Canada, July, 2018
  • R. Llorente, M. Morant, J.S. Bruno, V.Almenar, J.L. Corral, J.M. Fuster, J.Valls, “Multidimensional multiplexing in multicore fibre for hybrid optical backhaul provision: The XCORE approach”, 20th International Conference on Transparent Optical Networks (ICTON), 2018
  • P. Medina, V. Almenar, and J.L. Corral, “MIMO Equalization for Two-Mode Division Multiplexing over Standard SMF at 850 nm”, OSA Advanced Photonics Congress (Signal Processing in Photonic Communications), 2017
  • J.O. Lacruz, F. García-Herrero, M.J. Canet, J. Valls, A. Pérez-Pascual, “A 630 Mbps non-binary decoder for FPGA,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1989-1992, Lisbon, Portugal, May, 2015
  • F. Garcia-Herrero, D. Declercq, J. Valls, “ A symbol flipping decoder for NB-LDPC relying on multiple votes, ” 2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Bremen, Germany, Aug.2014
  • E. Li, D. Declercq, F. Garcia-Herrero, J. Omar, J. Valls, “ Low latency T-EMS decoder for NB-LDPC codes, ” Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, Nov.2013
  • F Garcia-Herrero, MJ. Canet, J. Valls, “ High-speed NB-LDPC decoder for wireless applications, ” Int.Symposium on Intelillent Signal Processing and Communication Systems (ISPACS), Okinawa, Japan, Nov.2013
  • V. Torres, A. Perez-Pascual, T. Sansaloni, J. Valls, “Fully-parallel LUT-based (2048,1723) LDPC Code Decoder for FPGA, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS),Sevilla, Spain, Dec.2012
  • F. Angarita, V. Torres, A. Perez-Pascual, J. Valls, “High-Throughput FPGA-based Emulator for Structured LDPC Codes, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • F. Garcia-Herrero, M.J. Canet, J. Valls, “Decoder for an Enhanced Serial Generalized Bit Flipping Algorithm, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • R. Gutierrez, J. Valls, A. Perez-Pascual, “FPGA-implementation of time-multiplexed multiple constant multiplication based on carry-save arithmetic, ” International Conference in Field Programmable Logic and Applications (FPL), Prague, Czech Republic, Aug.2009
  • J. Marín-Roig, V. Almenar, M.J. Canet, J. Valls, “64-QAM 4×4 MIMO Decoders Based on Successive Projection Algorithm, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS),Malta, Aug.2008
  • F. Angarita, M.J. Canet, T. Sansaloni, V. Almenar and J. Valls, “Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Marrakech, Morocco, Dec.2007
  • M.J. Canet, V. Almenar, J. Marin-Roig, J. Valls, “Time synchronization for the IEEE 802.11a/g WLAN Standard, ” 8th IEEE Annual International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC), Athens, Greece, Sep.2007
  • M.J. Canet, V. Almenar, S. Flores, J. Valls, “Improvement of a Time Synchronization Algorithm for IEEE 802.11a/G WLAN Standard, ” 15th European Signal Processing Conference (EUSIPCO),Poznan, Poland, Sep.2007
  • R. Gutierrez, J. Valls, “Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms, ” International Conference in Field Programmable Logic and Applications (FPL), Amsterdam, Holland, Aug.2007
  • V. Torres, T. Sansaloni, A. Perez-Pascual, J. Valls, “Design of high performance timing recovery loops for communication applications, ” 2006 IEEE Workshop on Signal Procesing Systems (SiPS), Banff, Canada, Nov.2006
  • M.J.Canet, I. Wassel, V. Almenar, J. Valls, “Performance evaluation of fine time synchronizer for WLANs, ” 13th european Conference on Signal Processing (EUSIPCO), Antalya, Turkey, Sep.2005
  • F. Angarita, T. Sansaloni, A. Pérez-Pascual, J. Valls, “FPGA-based design of a Viterbi decoder for WLAN, ” 2005 IEEE Workshop on Signal Processing Systems (SiPS), Atenas, Greece, Nov.2005
  • F. Angarita, T. Sansaloni, A. Pérez-Pascual, J. Valls, “Efficient FPGA implementation of CORDIC algorithm for circular and linear coordinates, ” International Conference in Field Programmable Logic and Applications (FPL), Tampere, Finland, Ago.2005
  • T. Todorovich, E. Boemo, F. Angarita, J. valls, “Statical power estimation for FPGAs, ” International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, Ago.2005
  • MJ.Canet, F. Vicedo, V. Almenar, J. Valls, “FPGA imlementation of an IF transceiver for OFDM-based WLAN, ” 2004 IEEE Workshop on Signal Processing Systems (SiPS 2004), Austin, Texas, Aug.2004
  • M.J.Canet, F. Vicedo, V. Almenar, J. Valls, E.R. De Lima, “Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2, ” International Conference in Field Programmable Logic and Applications (FPL), Antwerp, Belgium, Aug.2004
  • MJ. Canet, F. Vicedo, J. Valls, V. Almenar, “A common FPGA-based synchronizer architecture for hiperlan 2 and IEEE 802.11A WLAN systems, ” 15th International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Barcelona, Spain, Sep.2004
  • M.J.Canet, F. Vicedo, V. Almenar, J. Valls, E.R. De Lima, “Implementation of a Synchronizer for Hiperlan/2 on FPGA, ” International  Workshop on Telecommunications (IWT), Santa Rita do Sapucai, Brazil, Aug.2004
  • MJ. Canet, F. Vicedo, J. Valls, V. Almenar, “Design of a digital front-end transmitterfor OFDM-WLAN systems using FPGA, ” First International Symposium on Control, Communications and Signal Processing (ISCCSP), Hammamet, Tunisia, Mar.2004
  • E.R. de Lima, S.J. Flores, V. ALmenar, M.J. Canet, “Peformance Enhancements in OFDM-WLAN Systems Using MIMO Access Techniques, ” International Workshop on Telecommunications (IWT),Santa Rita do Sapucai, Brazil, Aug.2004
  • E.R. de Lima, S.J. Flores, V. ALmenar, M.J. Canet, “Performance Evaluation of MIMO-OFDM Systems Using Sphere Decoding Algorithm, ” The 60th Vehicular Technology Conference (VTC), Los Angeles, USA, Sep.2004
  • E.R. de Lima, S.J. Flores, V. ALmenar, M.J. Canet, “Analysis and Contrast between STC and Spatial Diversity Techniques for OFDM WLAN with Channel Estimation, ” International Conference on Telecommunications (ICT), Fortaleza, Brasil, Aug.2004
  • F. Cardells, J. Valls, “Quadrature Direct Digital Frequency Synthesizers: Area-optimized Design Map for LUT-based FPGAs, ” IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, May.2003
  • J. Marín-Roig, V.Torres, M.J.Canet, A.Pérez, T. Sansaloni, F. Cardells, F.Angarita, F.Vicedo, V.Almenar, J.Valls, “DIGIMOD: A tool to implement FPGA-based digital IF and baseband modems, ” International Conference on Field Programmable Logic and Applications (FPL), Lisbon, Portugal, Sep.2003
  • F. Cardells, J. Valls, V. Almenar, “Symbol Timing Synchronization in FPGA-based Software Radios: Application to DVB-S, ” 13th International Conference on Field Programmable Logic and Applications (FPL), Lisbon, Portugal, Sep.2003
  • F. Cardells, A. Perez-Pascual, V. Torres, J. Valls, V. Almenar, “Design of a DVB-S receiver in FPGA, ” 2003 IEEE Workshop on Signal Processing Systems (SiPS), Seoul, Korea, Aug.2003
  • J. Marín-Roig, V.Torres, M.J.Canet, A.Pérez, T. Sansaloni, F. Cardells, F.Angarita, F.Vicedo, V.Almenar, J.Valls, “DIGIMOD: A tool to implement FPGA-based digital front-end for software radios, ” Software Defined Radio Technical Conference and Product Exposition (SDR), Orlando, Florida, Nov.2003
  • F. Cardells, J. Valls, V. Almenar, V. Torres, “Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB standard, ” International Conference on Field Programmable Logic and Applications (FPL), Montpellier, France, Sep.2002
  • F. Cardells, J. Valls, “High Performance Quadrature Digital Mixers for FPGAs, ” International Conference on Field Programmable Logic and Applications (FPL), Montpellier, France, Sep.2002
  • José Marin-Roig, Javier Valls, Vicenç Almenar, “LUT-based Up-converters for FPGA, ” IEEE, IET International Symposium on Communication Systems, Networks and Digital Signal Processing Conference, Staffordshire, UK, Jul.2002
  • F. Cardells, J. Valls, “Optimized FPGA-implementation of quadrature DDS, ” IEEE International Symposium on Circuits and Systems (ISCAS), Arizona, USA, May.2002
  • A. Perez-Pascual, T. Sansaloni, J. Valls, “FPGA Based Radix-4 Butterflies for HIPERLAN/2, ” IEEE International Symposium on Circuits and Systems (ISCAS) Arizona, USA, May.2002
  • T. Sansaloni, A. Perez-Pascual, J. Valls, “Distributed Arithmetic Radix-2 Butterflies for FPGA, ” International IEEE Conference on Electronics, Circuits, and Systems (ICECS) (ICECS 2001)
  • A. Perez-Pascual, T. Sansaloni, J. Valls, “FPGA Based On-line Complex-Number Multipliers, ” International IEEE Conference on Electronics, Circuits, and Systems Malta, Sep.2001
  • J. Valls, M. Kuhlmann, K.K. Parhi, “Efficient mapping of CORDIC algorithms on FPGA, ” 2000 IEEE Workshop on Signal Processing Systems (SiPS), Louisiana, USA, Oct.2000
  • T. Sansaloni, J. Valls, K.K. Parhi, “Digit-Serial Fixed Coefficient Complex Number Multiplier-Accumulator on FPGAs, ” Annual IEEE International ASIC/SOC Conference, Washington, USA, Sep.2000
  • T. Sansaloni, and J. Valls, “FPGA-Based Digit-Serial Radix 2 Butterflies, ” IASTED International Conference Signal Processing and Communications (SPC), Marbella, Spain, Sep.2000
  • A. Pérez-Pascual, and J. Valls, “Radix-4 On-Line Complex-Number Multiplier, ” IASTED International Conference Signal Processing and Communications (SPC), Marbella, Spain, Sep.2000
  • T. Sansaloni, J. Valls, K.K. Parhi, “FPGA-based Digit-Serial Complex Number Multiplier-Accumulator, ” IEEE International Symposium on Circuits and Systems (ISCAS) Geneva, Switzerland. May.2000
  • J.Valls, T.Sansaloni, M.M.Peiró, E.Boemo, “Fast FPGA-Based Pipelined Digit-Serial/Parallel Multipliers, ” IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, USA, Jun.1999
  • A.P. Pascual, J.Valls, M. Martínez, “Efficient Complex-Number Multipliers mapped on FPGA, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Chipre, Sep.1999.>
  • T. Sansaloni, J.Valls, M.J. Canet, M. Martínez, “FPGA-based notch filter for cancelling 50Hz noise on ECGs, ” Design of Circuits and Integrated Systems Conference (DCIS), Mallorca, Spain, Nov.1999
  • M. M. Peiró, J. Valls, T. Sansaloni , A.P. Pascual, E. Boemo, “A Comparison between Lattice, Cascade and Direc-form FIR Filter Structures by using an FPGA Bit-serial Distributed Arithmetic Implementation, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS),Chipre, Sep.1999
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, “Design and FPGA implementation of Digit-Serial FIR filters, ” 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Lisbon, Portugal, Sep.1998
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, “A Study About FPGA-based Digital Filters, ” IEEE Workshop on Signal Processing Systems: Design and Implementation (SiPS), Boston, USA, Oct.1998
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, “Custom Digit-Serial DSPs on Altera FPGAs, ” Design of Circuits and Integrated Systems Conference (DCIS), Madrid, Spain, Nov.1998
  • M. Martínez, J.Valls,  T. Sansaloni, E. Boemo, “High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic, ” Design of Circuits and Integrated Systems Conference (DCIS), Madrid, Spain, Nov.1998
  • M. Martínez, J.Valls, E. Boemo, “On the design of PFGA-based multioperand pipeline adders, ” Design of Circuits and Integrated Systems Conference (DCIS), Sevilla, Spain, Nov.1997