This core implements a serial Reed-Solomon encoder for 8-bit wide symbols. Its more important features and implementation example results are shown below.
Reed-Solomon Encoder core features:
- Configurable Primitive Polynomial
- Variable number of parity symbols from 4 to 10
- Variable Generator Polynomial power value
- Valid for shortened length codes, from 54 to full length (255)
Implementation example
The Reed-Solomon Encoder core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:
- Primitive polynomial = 285 and 391
The following table shows the implementation results for the Virtex-6 device:
|
Pol=285
|
Pol=391
|
|
|---|---|---|
|
Number of slices
|
75
|
90
|
|
Number of RAMB18E1
|
1
|
1
|
|
Max. Clock Frequency
|
209.2 MHz
|
215.1 MHz
|
|
Throughput
|
83.6 Mbps
|
86.4 Mbps
|
The following table shows the implementation results for the Stratix-IV device:
|
Pol=285
|
Pol=391
|
|
|---|---|---|
|
Total LABs
|
21
|
21
|
|
M9K blocks
|
1
|
1
|
|
Max. Clock Frequency
|
228.7 MHz
|
234.5 MHz
|
|
Throughput
|
91.4 Mbps
|
93.8 Mbps
|