This core implements an Additive White Gaussian Noise generator based on the inverse of the Cumulative distribution function (iCDF). The core is implemented with a low complexity architecture using Tausworthe uniformly distributed random generators and memory-based interpolation. Its more important features and implementation example results are shown below.
AWGN Generator core features:
- Configurable uniformly distributed generator (URG): 64-bit or 128-bit
- High Gaussian distribution tail: 9.4σ with 64-bit or 13.3σ with 128-bit URG
- 18-bit output symbols width
Implementation example
The AWGN Generator core was implemented in a Xilinx Virtex-6 device (speed grade -3) and an Altera Stratix-IV (speed grade -4) device with the following features:
- uniformly distributed generator = 64-bit and 128-bit
The following table shows the implementation results for the Virtex-6 device:
|
64-bit
|
128-bit
|
|
|---|---|---|
|
Number of slices
|
115
|
179
|
|
Number of RAMB36E1
|
–
|
2
|
|
Number of RAMB18E1
|
2
|
1
|
|
Number of DSP48E1s
|
2
|
2
|
|
Max. Clock Frequency
|
297.1 MHz
|
255.4 MHz
|
|
Throughput
|
297.1 Msps
|
255.4 Msps
|
The following table shows the implementation results for the Stratix-IV device:
|
64-bit
|
128-bit
|
|
|---|---|---|
|
Total LABs
|
52
|
65
|
|
M9K blocks
|
2
|
3
|
|
DSP blocks 18-bit
|
4
|
4
|
|
Max. Clock Frequency
|
326.4 MHz
|
325.1 MHz
|
|
Throughput
|
326.4 Msps
|
325.1 Msps
|